Add full compiler toolchain, libc, examples and reference docs
First substantive commit: the entire Sprinter C compiler tree on top of
the bare README+gitignore initial commit.
What's in here:
bin/sprinter-cc — driver script invoking SDCC + linker + mkexe
libc/ — Sprinter-specific libc layer over ESTEX/BIOS
(conio, gfx, io, mem, stdio + headers)
runtime/ — crt0 variants (default/small/banked/minimal)
+ heap + bank trampolines
toolchain/ — mkexe (SprintEXE packer, C + tests)
examples/ — 30 demo programs (gfx, file I/O, env, time, …)
lib/Makefile — builds the libc archive (sprinter.lib)
docs/ — converted Sprinter manuals + asm reference samples
third_party/ — solid-c reference compiler dump + sdcc setup script
release_docs/ — packaging / release notes
gitignore overhaul:
• Drop dangerous blanket patterns: *.asm (would hide docs/samples/*.asm)
and *.exe (case-insensitive match was hiding third_party/solid-c/*.EXE
on macOS APFS). Replaced with examples/*/*.{asm,exe,…} and lib/*.lib.
• Restore tracking of toolchain/mkexe/tests/{one,big}.bin — those are
INPUT fixtures, not build outputs.
• Collapse the duplicated SDCC/C/Sdcc sections into one section per
concern (build outputs / vendored / OS-junk).
• Add .sprinter-cc-*/, build/ (catches lib/build/ too), .claude/.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
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/*
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* gfx_core.c — Sprinter graphics: common state + setup/teardown API.
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*
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* This module owns the variables that select which graphics page is
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* visible vs drawn into, which W3 bank is mapped during gfx writes,
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* and the row-base CPU address. All mode-specific primitives (256-
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* color in gfx_raw_256.c / gfx_256.c, 16-color in gfx_raw_16.c /
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* gfx_16.c, text in gfx_text_*.c) read this state via extern.
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*
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* Public API:
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* gfx_init / gfx_done — switch video mode, restore previous
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* gfx_set_visible_page / get — ESTEX $54 SELPAGE wrapper + cached value
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* gfx_set_draw_page / get — updates _gfx_addr_base for the new page
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* gfx_set_bank / get — sets the W3 page byte (0x50..0x5F)
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* gfx_wait_vsync — EI; HALT until next frame interrupt
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* gfx_pal_load / gfx_pal_set — BIOS $A4 PIC_SET_PAL wrappers
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*
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* Shared state (extern from this file):
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* _gfx_addr_base — 0xC000 for page 0, 0xC140 for page 1. Every
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* mode-specific primitive uses this instead of a
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* hard-coded 0xC000 so the same code targets the
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* currently-selected draw page.
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* _gfx_bank — read by _gfx_w3_video_begin in gfx_raw_common.c
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* to map the right W3 page.
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*/
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#include <gfx.h>
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#include <stdint.h>
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/* From conio's videomode_raw.c — bypasses set_videotextmode's text-only
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* validation so gfx_init can move INTO graphics modes. */
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extern uint8_t _videomode_raw_get(void);
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extern int _videomode_raw_set(uint8_t mode);
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/* ---- Shared graphics state --------------------------------------- */
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/* Cached values of the SELPAGE state. Page numbers are 0 or 1. */
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static uint8_t _gfx_visible_page = 0;
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static uint8_t _gfx_draw_page = 0;
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/* The W3 page byte (0x50..0x5F) — see memory/sprinter_vram_transparency.md
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* for the bit-meanings (0x50 normal, 0x54 temp, 0x58 transparent, 0x5C
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* both). Read by _gfx_w3_video_begin in gfx_raw_common.c. */
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uint8_t _gfx_bank = 0x50;
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/* CPU address of column 0 in the current draw page. Each VRAM row is
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* 1024 bytes wide — page 0 occupies bytes 0..319 (CPU 0xC000+), page 1
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* occupies 320..639 (CPU 0xC140+), and the remaining 384 bytes hold
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* mode descriptors / palette data we don't touch. Updated by
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* gfx_set_draw_page; read by every primitive's raw helper. */
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uint16_t _gfx_addr_base = 0xC000;
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/* ---- gfx_init / gfx_done ----------------------------------------- */
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uint8_t gfx_init(uint8_t mode, uint8_t page)
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{
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uint8_t prev = _videomode_raw_get();
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_videomode_raw_set(mode);
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_gfx_bank = 0x50;
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gfx_set_visible_page(page);
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gfx_set_draw_page(page);
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return prev;
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}
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void gfx_done(uint8_t mode)
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{
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_videomode_raw_set(mode);
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}
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/* ---- Visible page (ESTEX $54 SELPAGE) ---------------------------- *
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*
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* Direct OUT to port 0xC9 bit 0 toggles the "screen mode page" register
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* but doesn't notify DSS's display bookkeeping, leaving the screen in
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* an inconsistent state (one of the swaps shows as black). Going
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* through the syscall keeps DSS happy.
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*/
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void gfx_set_visible_page(uint8_t page)
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{
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_gfx_visible_page = page & 1;
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__asm
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push ix
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ld a, (__gfx_visible_page)
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ld b, a ; B = page 0/1
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ld c, #0x54 ; ESTEX SELPAGE
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rst #0x10
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pop ix
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__endasm;
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}
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uint8_t gfx_get_visible_page(void)
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{
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return _gfx_visible_page;
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}
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/* ---- Draw page --------------------------------------------------- */
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void gfx_set_draw_page(uint8_t page)
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{
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_gfx_draw_page = page & 1;
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/* Direct constants beat (0xC000 + (cond ? 0x140 : 0)) by 3 Z80
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* instructions — SDCC doesn't fold the constant addition. */
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_gfx_addr_base = _gfx_draw_page ? 0xC140 : 0xC000;
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}
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uint8_t gfx_get_draw_page(void)
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{
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return _gfx_draw_page;
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}
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/* ---- W3 bank (0x50..0x5F) ---------------------------------------- */
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void gfx_set_bank(uint8_t bank)
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{
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_gfx_bank = bank;
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}
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uint8_t gfx_get_bank(void)
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{
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return _gfx_bank;
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}
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/* ---- Frame sync -------------------------------------------------- *
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*
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* Block until the next IM2 frame interrupt (50 Hz, programmed by DSS
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* for keyboard / cursor maintenance). The Z80's HALT instruction
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* sleeps the CPU until the next IRQ, which DSS handles and returns
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* to the instruction after HALT — that's the start of the vertical
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* retrace window, ideal for a tear-free page swap.
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*/
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void gfx_wait_vsync(void) __naked
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{
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__asm
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ei
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halt
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ret
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__endasm;
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}
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/* ---- Palette (BIOS $A4 PIC_SET_PAL) ----------------------------- */
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static uint8_t pal_num_;
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static uint8_t pal_start_;
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static uint8_t pal_count_;
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static uint16_t pal_data_;
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void gfx_pal_load(uint8_t pal_num, uint8_t start, uint8_t count,
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const uint8_t *data)
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{
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pal_num_ = pal_num;
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pal_start_ = start;
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pal_count_ = count;
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pal_data_ = (uint16_t)(uintptr_t)data;
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__asm
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push ix
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ld a, (_pal_start_)
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ld e, a ; E = start
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ld a, (_pal_count_)
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ld d, a ; D = count (0 → 256)
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ld hl, (_pal_data_) ; HL = data
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ld b, #0xFF ; mask
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ld a, (_pal_num_) ; A = palette number
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ld c, #0xA4 ; BIOS PIC_SET_PAL
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rst #0x08
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pop ix
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__endasm;
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}
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void gfx_pal_set(uint8_t pal_num, uint8_t idx,
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uint8_t r, uint8_t g, uint8_t b)
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{
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uint8_t entry[4];
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entry[0] = b;
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entry[1] = g;
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entry[2] = r;
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entry[3] = 0;
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gfx_pal_load(pal_num, idx, 1, entry);
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}
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